Model-Based Engineering Research: Advanced Processor Performance
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Our objectives in this project are to
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The researchers involved in this project are
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What is required for the efficient use
of advanced processor hardware architectures
without sacrificing predictable execution times?
Because performance analysis of real-time and embedded systems relies on determinable and predictable resource demands that applications avoid over- and under-allocating CPU resources, the utilization efficiency depends on the ability to adequately determine the resource usage of the workload imposed on the system and allocate resources based on the estimated resource usage.
The trend is that real-time and embedded systems are increasingly deploying more advanced hardware CPU architectures. The architectures feature advanced multilevel caching, multistep pipelining, tightly connected CPUs, and the like, but their effects and their applicability to real-time and embedded systems have received little attention.
In this project, we are seeking engineering-based solutions with variation in a number of dimensions. This purpose requires us to better understand the combinatorial effects of cache architectures and pipeline depth, with respect to their temporal impact on software performance on single partition and multiple partitioned systems.
See also our other research projects
For More Information
Customer Engagements
Terry Dailey
Phone: 703-908-8213
E-mail: etd@sei.cmu.edu
Technical Questions
Jörgen Hansson
Phone: 412-268-6733
E-mail: hansson@sei.cmu.edu
Peter Feiler
Phone: 412-268-7790
E-mail: phf@sei.cmu.edu
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