Real-time and embedded systems are increasingly deploying more advanced hardware CPU architectures. The architectures feature advanced multilevel caching, multistep pipelining, tightly connected CPUs, and the like. But their effects and their applicability to real-time and embedded systems have received little attention.
What is required for the efficient use of advanced processor hardware architectures without sacrificing predictable execution times?
Performance analysis of real-time and embedded systems relies on determinable and predictable resource demands of applications on over- and under-allocating CPU resources. Thus, the utilization efficiency depends on the ability to adequately determine the resource usage of the workload imposed on the system and allocate resources based on the estimated resource usage.
In this project, we are engineering solutions with variation in a number of dimensions. This purpose requires us to better understand the combinatorial effects of cache architectures and pipeline depth with respect to their temporal impact on software performance on single partition and multiple partitioned systems.
Our objectives in this project are to
Read a presentation on performance challenges for advanced processor hardware.