Software Engineering Institute

“The performers in the DARPA ERI programs are of extremely high quality, in many cases the best in the world,” said John Wohlbier, a senior research scientist at the SEI. “We get the opportunity to help improve the technology not just from one group, but from several groups across several programs.”

Researchers from the SEI are working on new methods to evaluate hardware-software codesigns for individual applications and entire operational domains. Hardware-software codesign involves concurrently designing the hardware and software components of electronic systems. This process optimizes their performance under given size, weight, and power (SWaP) constraints. While hardware-software codesign is not a new concept, it is getting a fresh look due to the high demands that AI systems make on hardware.

Contributing to the ERI programs requires knowledge and expertise across the entire technology stack, including algorithmic applications such as graph analytics and machine learning; high-level programming languages such as Python, C, and C++; and compiler technologies, including abstract syntax trees and intermediate representations. It also requires knowledge of low-level language concepts such as assembler and instruction set architectures, as well as hardware ideas such as cycle-level performance considerations and design tools. Most organizations cannot field a team with such a broad skill set.

“Hardware-software codesign is a critical concept in designing systems for machine learning to enable better performance at lower power,” said DARPA’s Tom Rondeau, program manager for DARPA ERI’s Domain-Specific System on Chip (DSSoC) program. The SEI is helping DSSoC’s test and evaluation team. DSSoC is developing a system­-on-chip (SoC) to improve software performance within an operational domain. Applications within a domain have similar functional and system requirements. A processor tuned to the domain’s requirements would run the domain’s applications more efficiently than a general-purpose processor, without the difficulty and cost of building application-specific processors.

In contrast, the ERI’s Software Defined Hardware (SDH) program targets applications, including graph analytics, graph neural networks, and convolutional neural networks. Participants in the SDH program codesign hardware and software systems that reconfigure themselves in real time as they process application workloads. This adaptability enables performance that is nearly as good as Application Specific Integrated Circuits (ASICs) while maintaining programmability for data-intensive algorithms.

The SEI’s SDH team benchmarks DoD data-intensive mission workflows on a baseline platform. Team members evaluate the participants’ hardware and software platforms to determine the best architecture to process complex, data-intensive applications. The team’s results help DARPA decide which ERI software-defined hardware platforms to fund.

The SEI’s feedback on DSSoC and SDH improves the tools used by DARPA ERI participants, leading to better designs. Its input drives DARPA’s decisions about investments in future computing architectures.

To support this work, the SEI organized the Software-Hardware Codesign for Machine Learning Workloads workshop at MLSys 2020 in Austin, Texas. It featured talks from DARPA, startup companies for AI hardware, universities, national laboratories, and established chip vendors. “The timely hardware-software codesign workshop allowed us to communicate with an impressive list of speakers and attendees that will help us further expand our engagement with this community,” said Rondeau.