2021 Research Review / DAY 1
Spiral/AIML: Resource-Constrained Co-Optimization for High-Performance, Data-Intensive Computing
Commanders and warfighters in the field rely on data, and the Department of Defense and U.S. intelligence community have an overwhelming data collection capability. This capability far outpaces the ability of human teams to process, exploit, and disseminate information. Artificial intelligence (AI) and machine learning (ML) techniques show great promise for augmenting human intelligence analysis. However, most AI/ML algorithms are computationally expensive, data intensive, and difficult to implement efficiently in increasingly complex computer hardware and architectures. What’s more, moving very large amounts of data through tactical and operational military networks requires forward deployment of advanced AI/ML techniques to support commanders and warfighters in theaters with equipment constrained by cost, size, weight, and power (CSWAP).
If successful, our solution will allow platform developers to realize highperformance AI/ML applications on leading-edge hardware architectures faster and cheaper.
Col. Drew Cukor, USMC, observed, “Rapidly delivering artificial intelligence to a combat zone won’t be easy.” To address this challenge, the SEI is developing Spiral/AIML: Co-optimization for High-Performance, Data-Intensive Computing in Resource-Constrained Environments.
As the military adopts AI/ML to augment human teams, the cost of implementing and re-implementing AI/ML software on new hardware platforms will be prohibitive. To address these challenges, we propose to build on CMU’s Spiral technology, a hardware-software co-optimization system that will
- automatically search and select hardware configurations that meet CSWAP requirements
- automatically generate optimized codes for the selected hardware configuration and the irregular, data-intensive computations required for AI/ML algorithms
If successful, our solution will allow platform developers to realize high-performance AI/ML applications on leading-edge hardware architectures faster and cheaper. These advances will allow for rapid development and deployment of capabilities across the spectrum of national and tactical needs.
This FY2019-21 project
- builds on DoD line-funded research and sponsored work on automated code generation for future-compatible high-performance graph libraries, big learning benchmarks, GraphBLAS API specification, and graph algorithms on future architectures
- is related to a set of programs at the Defense Advanced Research Projects Administration (DARPA) under the Electronics Resurgence Initiative (ERI) umbrella (Hierarchical Identify Verify Exploit [HIVE], Software Defined Hardware [SDH], Domain Specific System on Chip [DSSoC], etc.) for which the CMU SEI has PWP work
- aligns with the CMU SEI technical objective to be affordable such that the cost of acquisition and operations, despite increased capability, is reduced and predictable and provides a cost advantage over our adversaries