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June 21, 2012—Advances in processor technology have shifted from faster processors to those that execute more instructions in parallel. These processors, called multicores, present challenges to software developers. Because multiple cores share memory, executing a function in one core can interfere with executing a function in another core. Stakeholders in the Department of Defense (DoD) and in industry fear multicore failure in systems such as aircraft and missiles, where lives are at stake.
"The consequences of defects in mission-critical systems could be
deadly, and the right answer delivered too late would become the wrong
answer." - Arie Gurfinkel, senior member of the SEI technical staff
Dionisio de Niz leads an SEI research effort to improve multicore processors. He explains that "for two cores performing two functions, execution times increase up to three times." Arie Gurfinkel, a teammate of de Niz, adds that "the consequences of defects in mission-critical systems could be deadly, and the right answer delivered too late would become the wrong answer." But the DoD will have to use multicores within 8 to 10 years, stressed team member Sagar Chaki, "because their ability to acquire single-core processors from chip manufacturers will run out."
Multicore processors do provide benefits. For instance, with multicores, developers can make advantageous tradeoffs regarding size, weight, and power. "Unmanned aerial vehicles (UAVs) are getting smaller and more agile," said de Niz, so they require more capabilities in fewer processors. Research, Technology, and System Solutions (RTSS) Program Director Linda Northrop noted that "multicore is the hardware of today, and it will be important for the DoD to exploit this technology."
The team is investigating several challenges of multicore programming. It's working on a technique using harmonic periods, which split task execution across two cores (migrating the task from one core to another) to prevent idle time in cores that cannot run a whole task. This maximizes the workload under strict deadlines and guarantees the same percentage of available processor capacity as in a single core.
SEI researcher Björn Andersson and collaborators from the Polytechnic Institute of Porto worked on software timing requirements. They developed a mode-change protocol for multicores with several operational modes, such as aircraft taxi, takeoff, flight, and landing modes. Andersson explained, "Our protocol is the first one that allows multicore software to switch modes while meeting all timing requirements. This lets software designers add or remove software functions while ensuring safety."
The multicore team is also working on power optimization. "UAVs, robots, and smartphones run on batteries, and warfighters can perform longer missions if batteries last longer," said team member Gabriel Moreno. Moreno and de Niz developed a new frequency-scaling algorithm that avoids processor partitions, so it can assign different speeds to individual cores. The method provides better power efficiency than was possible before.
"Multicore is the hardware of today, and it will be important for the
DoD to exploit this technology." - RTSS Program Director Linda Northrop
Chaki and Gurfinkel worked on migrating real-time, embedded systems from single-core to multicore platforms. They want to apply regression verification to help enable this migration. Regression verification determines the behavioral equivalence of two related programs so that the computation effort of verification is proportional to the amount of difference between the programs rather than to their size.
Addressing the challenges of multicore programming is crucial to the DoD and industry, and the team's work will help migration from single to multiple cores occur more safely and efficiently.
This article originally appeared in the 2011 SEI Year in Review. To download a copy of the SEI Year in Review, please visit http://www.sei.cmu.edu/library/abstracts/annualreports/2011-SEI-Year-in-Review.cfm.
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